Regviz

Espressif Systems /ESP32-S3 /INTERRUPT_CORE1 /CPU_INTR_FROM_CPU_0_MAP

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CPU_INTR_FROM_CPU_0_MAP

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/INTERRUPT_CORE1/CPU_INTR_FROM_CPU_0_MAP#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CPU_INTR_FROM_CPU_0_MAP

Description

cpu_intr_from_cpu_0 interrupt configuration register

Fields

CPU_INTR_FROM_CPU_0_MAP

this register used to map cpu_intr_from_cpu_0 interrupt to one of core1’s external interrupt

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data